Document - Compiling CHR to parallel hardware

2012

Conference article Open Access

Compiling CHR to parallel hardware

Triossi A., Orlando S., Raffaetà A., Fruhwirth T.

B.6 LOGIC DESIGN Parallelism CHR D.3.4 Processors Hardware acceleration

This paper investigates the compilation of a committed-choice rule- based language, Constraint Handling Rules (CHR), to specialized hardware circuits. The developed hardware is able to turn the intrin- sic concurrency of the language into parallelism. Rules are applied by a custom executor that handles constraints according to the best degree of parallelism the implemented CHR specification can of- fer. Our framework deploys the target digital circuits through the Field Programmable Gate Array (FPGA) technology, by first com- piling the CHR code fragment into a low level hardware description language. We also discuss the realization of a hybrid CHR inter- preter, consisting of a software component running on a general purpose processor, coupled with a hardware accelerator. The latter unburdens the processor by executing in parallel the most computa- tional intensive CHR rules directly compiled in hardware. Finally the performance of a prototype system is evaluated by time effi- ciency measures.

Source: 14th Symposium on Principles and Practice of Declarative Programming, pp. 173–184, Leuven, Belgium, 19-21 September 2012

Publisher: ACM Press, New York, USA

Metrics

Back to previous page

Cite as

BibTeX entry

@inproceedings{oai:it.cnr:prodotti:218846,
	title = {Compiling CHR to parallel hardware},
	author = {Triossi A. and Orlando S. and Raffaetà A. and Fruhwirth T.},
	publisher = {ACM Press, New York, USA},
	doi = {10.1145/2370776.2370798},
	booktitle = {14th Symposium on Principles and Practice of Declarative Programming, pp. 173–184, Leuven, Belgium, 19-21 September 2012},
	year = {2012}
}