Integrated performance models for SPMD applications and MIMD architectures
Cremonesi P., Gennaro C.
Single program multiple data (SPMD) Multiple instruction multiple (MIMD) Performance model Queuing network model Fork-join queues Mean value analysis (MVA) Parallel I/O Synchronization Speedup surface [Performance of systems]: modeling techniques [Processor architectures]: parallel architectures [Performance and reliability]: performance analysis and design aids [Input/output and data communications]: performance analysis and design aids
The report introduces queuing network models for the performance analysis of SPMD applications executed on general-purpose parallel architectures such as MIMD and clusters of workstations. The models are based on the pattern of computation, communication and I/O operations of typical parallel applications. Analysis of the models leads to the definition of speedup surfaces which capture the relative influence of processors and I/O parallelism and show the effects of different hardware and software components on the performance. Since the parameters of the models correspond to measurable program and hardware characteristics, the models can be used to predict the performance of parallel applications in early stages of software development.
Source: ISTI Technical reports, pp.1–19, 2001
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@techreport{oai:it.cnr:prodotti:160480,
title = {Integrated performance models for SPMD applications and MIMD architectures},
author = {Cremonesi P. and Gennaro C.},
institution = {ISTI Technical reports, pp.1–19, 2001},
year = {2001}
}
0000-0002-3715-149X